The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device excellent in reverse characteristic and a method of manufacturing the same.
In recent years, the use of a high voltage semiconductor element has been advanced. In general, in the high voltage semiconductor element, a ring-shaped EQR (equi-potential ring) electrode is formed to surround an active area in which cells are arrayed is formed. If a drain potential of the EQR electrode is kept, expansion of a depletion layer toward the outside of the cell area is suppressed. A mechanism in which the expansion of the depletion layer is suppressed is generally called “channel stopper mechanism”. The channel stopper mechanism is essential in obtaining an excellent reverse characteristic.
In a related-art high voltage semiconductor element, the EQR electrode includes two portions including a portion where the EQR electrode is formed on an interlayer insulating film, and a portion where the EQR electrode is embedded in the interlayer insulating film. Those two portions are electrically coupled to each other (Japanese Patent No. 3376209 and Japanese Patent No. 3440987). Also, there is a semiconductor element having a configuration in which the above two EQR electrodes are integrated together (Japanese Patent No. 4059566). Similarly, in this semiconductor element, a part of the EQR electrode is exposed to the interlayer insulating film.
A general high voltage semiconductor device will be described below. FIG. 13 is a plan view illustrating a configuration of a general high voltage semiconductor device 500. The semiconductor device 500 is of a rectangular contour, and has an active area 51 arranged in the center thereof. Cells such as MOSFETs (metal oxide semiconductor field effect transistor) are arranged in the active area 51. The active area 51 is covered with source electrodes (not shown) electrically coupled with the respective cells.
A ring-shaped second gate electrode 76 is formed apart from the active area 51 in an outer periphery of the active area 51. The second gate electrode 76 is electrically coupled to a first gate electrode 66 that will be described later. A ring-shaped second EQR electrode 73 is formed apart from the second gate electrode 76 in an outer periphery of the second gate electrode 76.
Subsequently, a cross-sectional structure of the semiconductor device 500 will be described. FIG. 14 is a cross-sectional view of the general high voltage semiconductor device 500 taken along a line XIV-XIV in FIG. 13. The semiconductor device 500 is sectioned into the active area 51 and a channel stopper area 52. In the semiconductor device 500, an n− type epitaxial layer 62 is formed over an n+ type semiconductor substrate 61. A drain electrode 69 is formed on a rear surface side of the semiconductor substrate 61.
In the active area 51, a p type base diffusion region 63 is formed in an upper portion of the epitaxial layer 62. On a part of an upper surface side of the base diffusion region 63 are formed an n+ type source diffusion region 64. A first gate electrode 66 is so formed as to apply a voltage to the base diffusion region 63 through a gate oxide film 65. An interlayer insulating film 67 is formed over the first gate electrode 66. A source electrode 68 that covers the active area 51 is electrically coupled to the source diffusion region 64.
In the channel stopper area 52, the base diffusion region 63 is formed in an upper portion of the epitaxial layer 62. An n+ type channel stopper layer 71 is formed on a part of an upper surface side of the base diffusion region 63. The channel stopper layer 71 is the same layer as that of the source diffusion region 64. The gate oxide film 65 is formed over the base diffusion region 63 and the epitaxial layer 62 where the channel stopper layer 71 is not formed. A first EQR electrode 72 is formed over the gate oxide film 65. The first EQR electrode 72 is covered with the interlayer insulating film 67. An opening portion is formed in a part of the interlayer insulating film 67, and an upper surface of the first EQR electrode 72 is exposed. The second EQR electrode 73, which is electrically coupled to the exposed first EQR electrode 72, is formed over the interlayer insulating film 67 and the channel stopper layer 71.
In an area between the active area 51 and the channel stopper area 52, a field oxide film 74 is formed over the epitaxial layer 62. The field oxide film 74 is covered with the interlayer insulating film 67. An opening portion is formed in the interlayer insulating film 67 formed over the first gate electrode 66 extending from the active area 51. The second gate electrode 76 is so formed as to be, electrically coupled to the first gate electrode 66 through the opening portion.
In the semiconductor device 500, when a reverse bias is applied between the source electrode 68 and the drain electrode 69, a depletion layer indicated by a broken line L1 expands toward the channel stopper area 52 from the active area 51.
On the other hand, in the channel stopper area 52, the channel stopper layer 71, the first EQR electrode 72, and the second EQR electrode 73 are electrically coupled to each other. Also, an end surface 75 of FIG. 14 is a surface formed by dicing and having a large number of defects. For that reason, the end surface 75 has an electrical conductivity. With this configuration, the channel stopper layer 71 and the drain electrode 69 are electrically connected to each other through the end surface 75. As a result, the first EQR electrode 72 is equipotential to the drain electrode 69.
When the first EQR electrode 72 is held to the drain potential, an inversion layer indicated by a broken line L2 is formed in the epitaxial layer 62 through the gate oxide film 65 formed below the first EQR electrode 72. With this configuration, a channel stopper structure is formed to stop an electric force line extending from the active area 51. As a result, in a voltage-current waveform, a hard breakdown shape (excellent reverse characteristic) is obtained.
Also, as another important characteristic of the high voltage semiconductor element, there are an on-resistance and a breakdown withstand voltage. The on-resistance mainly depends on a resistivity of the epitaxial layer, and can be reduced by increasing an impurity concentration in the epitaxial layer. However, when the impurity concentration of the epitaxial layer 62 increases, the breakdown withstand voltage decreases. That is, the on-resistance and the breakdown withstand voltage have a relationship of tradeoff. In order to avoid an influence of the tradeoff relationship, a cell shrink is applied to increase an on-state current per unit area so that a reduction in the on-resistance is realized.
On the other hand, there is a demand to reduce the on-resistance with the same chip size. To meet this demand, an attempt is made to enlarge a cell area (an area in which an element such as a transistor is formed). As one attempt, a method of reducing the channel stopper area has been proposed (Japanese Patent Application Publication No. 2008-270440).
Also, a technique in which a withstand voltage area (corresponding to the channel stopper area) is reduced with the use of a dead space of the semiconductor element has been proposed (Japanese Patent Application Publication No. 2008-193043). In this technique, a plurality of ring-shaped guard rings is formed over the semiconductor substrate around an active area. A ring-shaped first field plate having electric conductivity is formed over the guard ring. A second field plate formed of a metal film is formed over the guard ring. The second field plate is exposed to the interlayer insulating film. The second field plate is arranged on a portion of each corner of the semiconductor element in which the guard ring and the first field plate are curved. Since each corner of the semiconductor element is originally a dead space, the second field plate is arranged on the corner so that the width of the withstand voltage area can be narrowed, and the area of the active area can increase. Japanese Patent Application Publication No. Hei5(1993)-19010 and Japanese Patent No. 3417336 will be described later.